The order is not consistent in the SVD files. Some registers use an
ascending order, others descending. Make this consistent.
value = f' = 0x{register_value:X}'
print(f'{parent.name}_{register.name} @ 0x{addr:08X} (0x{base:08X} + 0x{offset:X}){value}:')
value = f' = 0x{register_value:X}'
print(f'{parent.name}_{register.name} @ 0x{addr:08X} (0x{base:08X} + 0x{offset:X}){value}:')
+ fields = sorted(register.get_fields(),
+ key=lambda x: x.bit_offset,
+ reverse=True)
- for f in register.get_fields():
if f.bit_width == 1:
bits = f'{f.bit_offset}'
name = f'{f.name}'
if f.bit_width == 1:
bits = f'{f.bit_offset}'
name = f'{f.name}'